The present invention relates to a CMOS FET IC (a Complementary Metal Oxide Semiconductor Field Effect Transistor Integrated Circuit) element and, more particularly to a CMOS FET IC element, having at least one pair of transistors, one an N channel MOS FET and one a P channel MOS FET, which selects a suitable signal level.
FIG. 1 shows a circuit diagram of a typical level selection circuit using N channel MOS FETs. This level selection circuit is used when a ROM (Read Only Memory) is the CMOS FET IC element, or when a chip selection signal level is chosen.
Referring to FIG. 1, in the case where a logic level of either an input terminal A1 (for example, a high logic level) or an input terminal B1 (for example, a low logic level) is selected, a threshold voltage of either N channel MOS FET Q1 or Q2 is set larger than a voltage +Vcc that is supplied to the gate of each N channel MOS FET Q1 and Q2 by using a P type ion implantation with a photomask, so that the N channel MOS FET that is implanted by the P type ion is of a type that is normally OFF and a source-drain current of the N channel MOS FET that is implanted by the P type ion cannot flow even when the voltage Vcc is applied. For example, when a logic level of the input terminal A1 is outputted at an output terminal C1, a threshold voltage Vth2 of the N channel MOS FET Q2 is set to be greater than the voltage Vcc by P type ion implantation, the N channel MOS FET Q2 is normally OFF, so that the source-drain current of the N channel MOS FET Q2 does not flow even when the voltage Vcc is applied. Therefore, when the voltage Vcc is applied and becomes greater than a threshold voltage Vthl of the N channel MOS FET Q1 without the implanted ion, the N channel MOS FET Q1 is turned ON, and the source-drain current of the N channel MOS FET Q1 flows, so that the output terminal C1 is charged by the source-drain current of the N channel MOS FET Q1 and the voltages of the output terminal C1 and the input terminal A1 are not equal. Accordingly, the logic level of the input terminal A1 is outputted at the output terminal C1.
On the contrary, when a logic level of the input terminal B1 is to be outputted at the output terminal C1, the threshold voltage Vth1 of the N channel MOS FET Q1 is set greater than the voltage Vcc by P type ion implantation and the N channel MOS FET Q1 is normally OFF, so that the source-drain current of the N channel MOS FET Q1 cannot flow even when the voltage Vcc is applied. Therefore, when the voltage Vcc is applied and becomes greater than the threshold voltage Vth2, the MOS FET Q2 is turned ON, and the source-drain current of the N channel MOS FET Q2 without the implanted ion flows, so that the output terminal C1 is charged by the source-drain current of the N channel MOS FET Q2 and the voltages of the output terminal C1 and the input terminal B1 are equal. Accordingly, the logic level of the input terminal B1 is outputted from the output terminal C1.
In the above level selection circuit, for example, in the case where the logic level (the high logic level) of the input terminal A1 is outputted from the output terminal C1, a logic level corresponding to a voltage obtained by subtracting the threshold voltage Vthl of the N channel MOS FET Q1 from the voltage corresponding to the logic level of the input terminal A1, is outputted at the output terminal C1. Accordingly, when the output of an inverter is to be inverted in response to the logic level of the output terminal C1, it cannot be inverted because the logic level of the output terminal C1 is lower than the logic level by an amount corresponding to the threshold voltage Vth1. Therefore, a level rectifying circuit is additionally required.